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1/3 inch sxga cmos image sensor S5K3A1EA 1 S5K3A1EA (1/3? sxga cmos image sensor) preliminary specification revision 0.4 jun, 2004
S5K3A1EA 1/3? sxga cmos image sensor 2 document title 1/3? optical size 1280x1024(sxga) 2.8v / 1.8v cmos image sensor revision history revision no. history draft date remark 0.0 initial draft feb.03, 2004 preliminary 0.1 dc characteristics changed. mar.29.2004 0.2 register map updated. apr.09.2004 0.3 imaging characteristics changed jun.10.2004 0.4 imaging characteristics changed jun.11.2004 S5K3A1EA13 product added ac characteristics changed ob_area recommended setting changed
1/3 inch sxga cmos image sensor S5K3A1EA 3 introduction the S5K3A1EA is highly integrated single chip cmos image sensor, fabricated by samsung 0.18um cmos image sensor process technology. it is developed for image application to realize high efficiency photo sensor. the sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. the sensor has on-chip 10-bit adc blocks to digitize the pixel output and also on-chip cds to reduce fixed pattern noise (fpn) drastically. with its few interface signals and 10-bit raw data directly connected to the external devices, a camera system can be configured easily. features ? process technology: 0.18 m dual gate oxide spqm cmos ? optical size: 1/3 inch ? unit pixel: 3.8 m x 3.8 m ? effective resolution: 1280x1024, sxga ? line progressive read out. ? 10-bit raw image data output ? windowing and panning ? sub-sampling (2x, 4x, 8x) ? timing generator for frame memoryless scaler ? timing generator for stepless zooming ? continuous and single frame capture mode ? programmable exposure time and gain control ? auto dark level compensation ? standby mode for power saving ? maximum 15 frames per second for full fram e readout with 24 mhz output data rate ? bad pixel replacement ? dual power supply voltage: 2.8v/1.8v (2.8v for analog, 1.8v for digital) ? package type: 48-clcc/plcc products product code power supply backend process description S5K3A1EA01 2.8v / 1.8 v none monochrome image sensor S5K3A1EA02 2.8v / 1.8 v on-chip micro lens high sensitivity monochrome image sensor S5K3A1EA03 2.8v / 1.8 v on-chip color filter and micro lens rgb color image sensor S5K3A1EA13 2.8v / 1.8 v on-chip color filter and micro lens rgb color image sensor
S5K3A1EA 1/3? sxga cmos image sensor 4 block diagram timing generator rstn stbyn mclk vsync hsync dclk scl sda strb main clock divider i 2 c interface control registers active pixel sensor array row driver even column cds odd column cds 10-bit column adc 10-bit column adc vddd vssd vdda vssa post processing data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 vddio vssio
1/3 inch sxga cmos image sensor S5K3A1EA 5 pixel array map (top view on chip. displ ayed image will be flipped.) active pixels optical black pixels (14,14) read out start point (0,0) default window of interest 1280x1024 10 4 r b g g 10 4 r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g 10 4 4 r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g 10
S5K3A1EA 1/3? sxga cmos image sensor 6 pin configuration 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 6 5 4 3 2 1 48 47 46 45 44 43 31 32 33 34 35 36 37 38 39 40 41 42 data8 data7 data6 data5 data4 data3 data2 data1 sda scl rstn stbyn strb vdda vssa test1 hsync vsync vssio first readout pixel data0 data9 mclk dclk vssd vdda vssa vssa vdda vdda vssa vssa vdda vddd vssd vddio vddd vdda vssa vssa vdda vdda vssa vssa vdda vddd vssd test2 vref
1/3 inch sxga cmos image sensor S5K3A1EA 7 maximum absolute ratings characteristic symbol value unit analog maximum absolute voltage (vdda supply relative to vssa ) v ddh -0.3 to 3.8 v digital and i/o maximum absolute voltage (vddio supply relative to vssio vddd supply relative to vssd) v ddl -0.3 to 2.7 input voltage v in -0.3 to 2.7 operating temperature t opr -20 to +60 c storage temperature t stg -40 to +125 (1) -40 to +85 (2) notes: 1. the maximum allowed storage temperature for S5K3A1EA01. 2. the maximum allowed storage temperat ure for S5K3A1EA02 and S5K3A1EA03.
S5K3A1EA 1/3? sxga cmos image sensor 8 electrical characteristics dc characteristics (t a = -20 to +60 c, c l = 15pf) characteristics symbol condition min typ max unit operating voltage v ddh applied to vdda pins 2.6 2.8 3.0 v v ddl applied to vddio and vddd pin 1.65 1.8 1.95 input voltage (1) v ih - 1.27 - - v il - - - 0.57 input leakage current (2) i il v in = v ddl -10 - 10 a input leakage current with pull-down (3) i ild v in = v ddl 5 18 40 v oh i oh = -1 a v ddl - 0.05 - - v high level output voltage (4) i oh = -4ma 1.2 - - v ol i ol = 1 a - - 0.05 low level output voltage (5) i ol = 4ma - - 0.45 high-z output leakage current (6) i oz v out = v ss or v ddl -10 - 10 a input capacitance (1) c in - - - 4 pf i stbl stbyn=low(active) all input clocks = low 0 lux illumination applied to vddio and vddd pin - - 10 a supply current i stbh stbyn=low(active) all input clocks = low 0 lux illumination applied to vdda pin - - 10 a i ddl f mclk = 12mhz 0 lux illumination applied to vddio and vddd pin - 10 15 ma i ddh f mclk = 12mhz 0 lux illumination applied to vdda pin - 20 25 ma notes: 1. applied to mclk, rstn, stbyn, strb, scl, sda, test1, test2 pins. 2. applied to mclk, rstn, stbyn, strb, scl, sda pins 3. applied to test1, test2 pin 4. applied to dclk, hsync, vsync, data0 to data9 pin. i oh : high level output current 5. applied to dclk, hsync, vsync, data0 to data9, scl, sda pin. i ol : low level output current 6. applied to sda pin w hen in high-z output state
1/3 inch sxga cmos image sensor S5K3A1EA 9
S5K3A1EA 1/3? sxga cmos image sensor 10 imaging characteristics (light source with 3200k of color temperature and ir cu t filter (cm-500s, 1mm thick ness) is used. electrical operating conditions follow the recommended typical values. the control registers are set to the default values. t a = 25 c if not specified.) notes: 1. measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7x7 rank filter is applied for the whole pixel area to eliminate the va lues from defective pixels. 2. measured average output at 25% of saturation level illumination for exposur e time 1/30 sec. green channel output values are used for color version. 3. measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark leve l rms noise excluding fixed pattern noi se). 60db is limited by 10-bit adc. 5. 20 log (average output level / rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. difference between maximum and minimum pi xel output levels at zero illumination for exposure time 1/30 sec. 7x7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 7, difference between maximum and minimum pixel output levels divided by average out put level at 25% of saturation level illumination for exposure time 1/30 sec. 7x7 median filter is applied for the whole pi xel area to eliminate the values from defective pixels. 8. for the column-averaged pixel output values, maximum relative deviation of values from 7- depth median filtered values for neighboring 7 columns at 25% of saturation le vel illumination for exposure time 1/30 sec. 9. for the row-averaged pixel output values, maximum relative deviation of values from 7-dept h median filtered values for neighboring 7 rows at 25% of saturation leve l illumination for exposure time 1/30 sec. characteristic symbol condition min typ max unit saturation level (1) v sat - 600 650 - mv sensitivity (2) s - - 1500 - mv/lux sec dark level (3) v dark t a = 40 c - 4 8 mv/sec t a = 60 c - 20 40 dynamic range (4) dr - - 60 - db signal to noise ratio (5) s/n - - 40 - dark signal non-uniformity (6) dsnu t a = 60 c - - 40 mv/sec photo response non- uniformity (7) prnu - - 4 8 % vertical fixed pattern noise (8) vfpn - 4 8 % horizontal fixed pattern noise (9) hfpn - 4 8 %
1/3 inch sxga cmos image sensor S5K3A1EA 11 ac characteristics (v ddh = 2.8v 0.25v, v ddl = 1.8v 0.15v, t a = -20 to + 60 c, c l = 10pf) notes: 1. t mclk is the period of the ma ster input clock, mclk. characteristic symbol condition min typ max unit main input clock frequency f mclk duty = 50% 6 12 48 mhz data output clock frequency f dclk - 6 12 30 t pdmv vsync output - - 10 ns propagation delay time from main input clock t pdmh hsync output - - 10 t pdmd dclk output - - 6 t pdmo data output - - 10 t pddv vsync output - - 4 propagation delay time from data output clock t pddh hsync output - - 4 t pddo data output - - 4 reset input pulse width t wrst rstn=low(active) 5 - - t mclk (1) standby input pulse width t wstb stbyn=low(active) 4 - - t pdmd data mclk dclk 0.5v dd hsync vsync t pddo t pdmo t pdmd t pddh t pdmh t pddh t pdmh t pddv t pdmv
S5K3A1EA 1/3? sxga cmos image sensor 12 i 2 c serial interface characteristics (1) notes: 1. i 2 c is a proprietary phillips interface bus. 2. t mclk is the period of the ma ster input clock, mclk. characteristic symbol condition min typ max unit clock frequency f scl - - - 400 khz clock high pulse width t wh scl 0.6 - - s clock low pulse width t wl scl 1.3 - - clock rise/fall time t r /t f scl, sda - - 0.3 data set-up time t ds sda to scl 0.1 - - data hold time t dh scl to sda - - 0.9 start condition setup time t strs - 4 t mclk (2) start condition hold time t strh - 4 stop condition setup time t stps - 4 - - stop to new start gap t gss - 8 - - capacitance for each pin c pin scl, sda - - 4 pf capacitive bus load c bus scl, sda - - 200 pull-up resistor r pu scl, sda to v dd 1.5 - 10 k ? sda scl 0.1v dd 0.9v dd t strs t strh t wl t dh t wh t ds t f t r 0.1v dd 0.9v dd t stps rstn stbyn t wstb t wrst mclk system reset partial power down complete power down
1/3 inch sxga cmos image sensor S5K3A1EA 13 pin description pin no i/o name function vddd (6,25,48) power digital power supply for logical circuit (v ddl ) vddio (5) power for i/o circuit (v ddl ) vssd (19,26,47) power 0v (gnd) vssio (20) power 0v (gnd) vdda(1,4,21,24, 28,29,37,44,45) power analog power supply for analog circuit (v ddh ) vssa(2,3,22,23, 27,30,36,43,46) power 0v (gnd) mclk (7) i master clock master clo ck pulse input for all timing generators. rstn (40) i reset initializing all the device register s. (active low) stbyn (39) i standby activating power saving mode. ( high=normal operation, low=power saving mode ) strb (38) i strobe triggering the integration start and stop when single frame capture mode. data0~data9 (8 ~ 17) o image data output 10-bit image data outputs. when adc resolution is reduced, the unused lower bits are set to 0. dclk (18) o data clock image data output synchronizing pulse output. hsync (32) o horizontal sync clock horiz ontal synchronizing pulse or data valid signal output. vsync (31) o vertical sync clock vertical synchronizing pulse or line valid signal output. scl (41) i serial interface clock i2c serial interface clock input sda (42) i/o serial interface data i2c serial interface data bus (external pull-up resistor required) vref (35) i/o reference voltage for proper oper ation, the external capacitor larger than 0.1uf must be connected between vref and vdda. test1 (33) i test input 1 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. test2 (34) i test input 2 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
S5K3A1EA 1/3? sxga cmos image sensor 14 control registers address (hex) reset value bits mnemonic description [7] p2_r_con (factory use only) cds timing control [6] bprm bad pixel replacement mode 0b: disabled (default), 1b: enabled [5] ccsm color channel separation mode 0b: not separated (default), 1b: separated [4:2] mcdiv main clock divider 000b: dclk=mclk(default), 001b: dclk=mclk 2 010b: dclk=mclk 4, 011b: dclk=mclk 8 100b: dclk=mclk 16, 101b: dclk=mclk 32 111b: forbidden value [1] shutc electronic shutter mode 0b: disabled (default), 1b: enabled 00h 01h [0] adcres adc resolution 0b: 8-bit, 1b: 10-bit (default) [7] shut_err_cor shutter error correction register [6] not_use [5] mircv vertical mirror control 0b: normal (default), 1b: mirrored [4] mirch horizontal mirror control 0b: normal (default), 1b: mirrored [3:2] subsr row sub-sampling mode 00b: disabled (default), 01b: 2x, 10b: 4x, 11b: 8x 01h 00h [1:0] subsc column sub-sampling mode 00b: disabled (default), 01b: 2x, 10b: 4x, 11b: 8x 02h 00h [2:0] wrp_high 03h 0eh [7:0] wrp_low row start point for window of interest wrp[10:0] = 14d(default) 04h 00h [2:0] wcp_high 05h 0eh [7:0] wcp_low column start point for window of interest wcp[10:0] = 14d(default) 06h 04h [2:0] wrd_high 07h 00h [7:0] wrd_low row depth for window of interest wrd[10:0] = 1024d(default) 08h 05h [2:0] wcw_high 09h 00h [7:0] wcw_low column width for window of interest wcw[10:0] = 1280d(default) 0ah 80h [7:0] offsdef (factory use only) analog offset reference offsdef[7:0] = 128d (default)
1/3 inch sxga cmos image sensor S5K3A1EA 15 address (hex) reset value bits mnemonic description 0bh 04h [7:0] sint_high 0ch 65h [7:0] sint_low integration time in single frame capture mode sint[15:0] = 1125d (default) 0dh 04h [7:0] cintr_high 0eh 65h [7:0] cintr_low row-step integration time in continuous frame capture mode cintr[15:0] = 1125d (default) 0fh 00h [7:0] cintc_high 10h 00h [7:0] cintc_low column-step integration time in continuous frame capture mode cintc[15:0] = 0d (default) [7] hspolar hsync polarity 0: active high (default), 1: active low [6] hsdisp hsync display mode 0: sync mode (default), 1: data valid mode [5] vspolar vsync polarity 0: active high (default), 1: active low [4] vsdisp vsync display mode 0: sync mode (default), 1: data valid mode [3] global_mod single frame capture integration mode field shift shutter mode [2] roll_mod single frame capture integration mode rolling shutter mode [1] mech_mod single frame capture integration mode simultaneous frame integration with mechanical shutter 11h 00h [0] sfcen single frame capture mode enable 0b: disabled (default), 1b: enabled 12h 01h [7:0] vswd vsync width vswd[7:0] = 1d (default) 13h 00h [7:0] vsstrt_high 14h 00h [7:0] vsstrt_low vsync start position vsstrt[9:0] = 0d (default) 15h 00h [7:0] vblank_high 16h 65h [7:0] vblank_low vertical blank depth vblank[12:0] = 101d (default) 17h 20h [7:0] hswd hsync width hswd[7:0] = 32d (default) 18h 00h [7:0] hsstrt_high 19h 00h [7:0] hsstrt_high hsync start position hsstrt[9:0] = 0d (default) 1ah 00h [7:0] hblank_high 1bh 8eh [7:0] hblank_low horizontal blank depth hblank[15:0] = 142d (default)
S5K3A1EA 1/3? sxga cmos image sensor 16 address (hex) reset value bits mnemonic description 1ch 00h [6:0] pgcr red channel gain pgcr[6:0] = 0d (default) 1dh 00h [6:0] pgcg1 green(red row) channel gain or all channel gain ( ccsm =0) pgcg1[6:0] = 0d (default) 1eh 00h [6:0] pgcg2 green(blue row) channel gain pgcg2[6:0] = 0d (default) 1fh 00h [6:0] pgcb blue channel gain pgcb[6:0] = 0d (default) 20h 0fh [4:0] sgg1 1 st quadrisectional global gain sgg1[4:0] = 0f(default) 21h 0fh [4:0] sgg2 2 nd quadrisectional global gain sgg2[4:0] = 0f(default) 22h 0fh [4:0] sgg3 3 rd quadrisectional global gain sgg3[4:0] = 0f(default) 23h 0fh [4:0] sgg4 4 th quadrisectional global gain sgg4[4:0] = 0f(default) 24h 80h [7:0] offsr red channel analog offset offsr[7:0] = 128 (default) 25h 80h [7:0] offsg1 green(red row) channel analog offset or all channel offset ( ccsm =0) offsg1[7:0] = 128 (default) 26h 80h [7:0] offsg2 green(blue row) channel analog offset offsg2[7:0] = 128 (default) 27h 80h [7:0] offsb blue channel analog offset offsb[7:0] = 128 (default) [7] clipen (factory use only) reset clipping enable 28h 14h [6:0] pthresh bad pixel threshold pthresh[6:0] = 20d (default) 29h 00h [7:0] adcoffs adc offset (count delay register) adcoffs[7:0] = 0d (default) adlc formula : d final = d(n) + adcoffs when adcoffs[7] is 1 , adc offset is +adcoffs[6:0], else adc offset is - adcoffs[6:0]
1/3 inch sxga cmos image sensor S5K3A1EA 17 address (hex) reset value bits mnemonic description [7:5] stbystrt (factory use only) stand-by start 2ah 40h [4:0] stbystp (factory use only) stand-by stop 2bh 00h [7:0] rxstrt (factory use only) reset start control 2ch 00h [7:0] blank blank register for general purpose [7:6] not_use [5] id_inv (factory use only) line color inversion [4] sck_inv (factory use only) column color inversion [3:2] not_use [1] i2ctest (factory use only) iic test mode 2dh 02h [0] nandtree (factory use only) nand tree test mode [7] adlc_mod_d adlc mode always enable when this register is high. 0b: disabled (default), 1b: enabled [6] adlc_mod_c adlc mode works when gain values are changed 0b: disabled (default), 1b: enabled [5] adlc_mod_b adlc mode works when shutter values are changed 0b: disabled (default), 1b: enabled [4] adlc_mod_a adlc mode works till adlc length value 0b: disabled (default), 1b: enabled [3:2] feedback_gain_b feedback gain value about adlc 00b : 0, 01b : 0.5(default), 10b : 0.75, 11b : 1 adlc formula : d final = d(n) + adcoffs d(n) = a*(ob(n) + ob(n-1)) + b*d(n-1) 2eh 06h [1:0] feedback_gain_a feedback gain value about adlc 00b : 0, 01b : 0.5, 10b : 0.25(default), 11b : 0.125
S5K3A1EA 1/3? sxga cmos image sensor 18 address (hex) reset value bits mnemonic description [7] dckout_en dck pad control 0b : output enable (default), 1b : stable value [6] dfo i/o driver fan-out control register. [5] fixvs vsync always high at frame start point. 0b: disabled (default), 1b: enabled [4] isp_sel (factory use only) [3] ob_sel adlc formula : d = d(n) + adcoff d(n) = a*(ob(n) + ob(n-1)) + b*d(n-1) 0b : ob(n-1) = ob(n-1) (default) 1b : ob(n-1) = ob(n) [2] ob_area ob area selection 0b:128*8 (default), 1b:512*2 (recommended) 2fh 00h [1:0] adlc_length adlc function works only during this value when adlc_mod_a enabled, 00b : 1 frame, 01b : 2 frames, 10b : 3 frames, 11b : 4 frames [7:6] not_use [5] pwr_save2 (factory use only) rx & tx signals are enable only active area. 0b: disabled (default), 1b: enabled [4] pwr_save1 (factory use only) 0b: disabled (default), 1b: enabled [3] ggo_en (factory use only) 0b: disabled (default), 1b: enabled [2] rsm_en (factory use only)when this register is zero, h-sync keeps same period in one frame. [1] gbmod guardband mode 0b: disabled, 1b: enabled(default) 30h 02h [0] stpless_mod stepless mode enable 0b: disabled (default), 1b: enabled 31h 1eh [7:0] gb_start guardband start position 32h 32h [7:0] gb_end guardband end position 33h 00h [5:0] vs_postc_high 34h 00h [7:0] vs_postc_low keep the same frame in zoom mode. this register compensates remainder of frame. [7:4] p12_stp (factory use only) cds timing control 35h cch [3:0] p11_stp (factory use only) cds timing control [7:4] p2r_stp (factory use only) cds timing control 36h cch [3:0] p2_stp (factory use only) cds timing control
1/3 inch sxga cmos image sensor S5K3A1EA 19 address (hex) reset value bits mnemonic description 37h 00h [7:0] holdline_high 38h 00h [7:0] holdline_low active output delay about its register value 39h 0ah [7:0] vsend_ofset-high this register value is must larger than ob line. [7] not use [6] tx_add (factory use only)add tg to reduce nit. [5] shutx_sel (factory use only)enlarge shutter tx width to reduce nit. [4] cal_en (factory use only) calibration enable 3ah 1ah [3:0] cal_stp (factory use only) calibration signal control
S5K3A1EA 1/3? sxga cmos image sensor 20 window of interest ( wcp , wrp ) wcw wrd 0 1307 1051 0 operation description 1. output data format 1-1. main clock divider all the data output and sync signals are synchronized to data clock output ( dclk ). it is generated by dividing the input main clock ( mclk ). the dividing ratio is 1, 2, 4, 8, 16, and 32 according to main clock dividing control register ( mcdiv ). for 10-bit adc and sxga resolution, dividing ratio of 1 is required. if dividing ratio of 1 is used, the duty must be within 40% to 60%. 1-2. synchronous signal output the horizontal sync( hsync ) and vertical sync( vsync ) signals are also available. the sync pulse width, polarity and position are programmable by control regist ers (ref. timing chart). when display mode is enabled, the sync signal outputs indicate t hat the output data is valid ( hsdisp =1) or the output rows are valid ( vsdisp =1). 1-3. window of interest control window of interest (woi) is defined as the pixel address range to be read out. the woi can be assigned anywhere on the pixel array. it is compos ed of four values: row start pointer( wrp ), column start pointer( wcp ), row depth( wrd ) and column width( wcw ). each value can be programmed by c ontrol registers. for convenience of color signal processing, wcp is truncated to even numbers so that t he starting data of each line is the red and green column of bayer pattern. figure 1 refers to a pict orial representation of the woi on the displayed pixel image. figure 1. woi definition. 1-4. vertical mirror and horizontal mirror mode control the pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction normally. by changing the mirror mode, the read-out sequence can be reversed and the resulting image can be flipped like a mirror image. pixel data are read out from ri ght to left in horizontal mirror mode and from bottom to top in vertical mirror mode. the horizontal and the vert ical mirror mode can be programmed by horizontal mirror control register ( mirch ) and vertical mirror control register ( mircv ). 1-5. sub-sampling control the user can read out the pixel data in sub-sampling rate in both horizontal and vertic al direction. sub-sampling can be done in four rates : full, 1/2, 1/4 and 1/8. the user controls the sub-sampling using the sub-sampling
1/3 inch sxga cmos image sensor S5K3A1EA 21 control registers, subsr and subsc . the sub-sampling is performed only in the bayer space. in figure 2, the bayer space sub-sampling examples are shown. figure 2. bayer space sub-sampling examples 1-6. line rate and frame rate control (virtual frame) the line rate and the frame rate can be changed by varying t he size of virtual frame. the virtual frame?s width and depth are controlled by effective woi and blank depths . the effective woi is scaled by the subsampling factors from woi set by register values. for cds and adc function, the virtual column width must be larger than ( adcres +1)*256/(2^ mcdiv )+264, where adcres is the adc resolution control r egister value. the horizontal and vertical blanking time ( hblank , vblank ) should be over 60 and 4, respectively. the detailed restriction of h-blank period is shown in table 1. table 1. restriction of h-blank period (minimum 1h-period(dck) minimum 1h-period(dck) mcdiv[2:0] adcres = 1 adcres = 0 0 1412 548 1 836 404 2 548 332 3 404 300 4 332 278 5 300 270 setting procedure of hblank, vblank and vs_postc is as follows. frame cycle = ((wcw>>subsc) + hblank) x ((wrd>>subsr) + vblank) + vs_postc vblank >= 4 (isp_sel=1) vs_postc < 1h ( (wcw>>subsc) + hblank) ) 1-7. continuous frame capture mode(cfcm) integrat ion time control (electronic shutter control) subsr =01b, subsc =01b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b subsr =00b, subsc =10b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b
S5K3A1EA 1/3? sxga cmos image sensor 22 in cfcm operation, the integration time is controll ed by shutter operation. the shutter operation is done when shutter control register ( shutc ) is set to ?1?. in shutter operation, t he integration time is determined by the row step integration time control register( cintr ) and column step integration time control register( cintc ) in cfcm integration time control. there are two diffe rent modes. one is normal shutter mode. the other is shutter tx wide mode to reduce nonlinear integration time. the effective integration time(eit) formulas of each mode are as follows. 1) normal mode (00h[2] = 1, 01h[7] = 1, 3ah[5] = 1) eit = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck) restriction of cintr? 1 <= cintr <= (wrd>>subsr) + vblankr ?1 restriction of cintc? 0 <= cintc <= (wcw>>subsc) + hblank - 7 2) shutter tx wide mode (00h[2] = 1, 01h[7] = 0, 3ah[5] = 1) eit = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck) restriction of cintr? 1 <= cintr <= (wrd>>subsr) + vblankr - 1 restriction of cintr? case of (1 <= cintr <= (wrd>>subsr) + vblankr - 2) 0 <= cintc <= (wcw>>subsc) + hblank - 7 case of (cintr = (wrd>>subsr) + vblankr - 1) 0 <= cintc <= (wcw>>subsc) + hblank - 195 1-8. single frame capture mode(sfcm) integration time control to capture a still image, sfcm can be se t by single frame capture enable register( sfcen ). there are two types of integration mode implement ed. in the rolling shutter mode ( sfcim =0), the integration time is controlled by sfcm integration time register ( sint ). the light integration period for each rows progresses with reading rows. the integration time is expressed as : integration time = sint * (1 line time) in the mechanical shutter mode ( sfcim =1), the integration time for all rows is the period during the external input signal, strb is active. after strb goes to be inactive, the external mec hanical shutter should shut off incident lignt on image sensor and the data readout sequence starts. 2. analog to digital converter ( adc) the image sensor has on-chip adc. two-channel co lumn parallel adc scheme is used for separated color channel gain and offset control. 2-1. adc resolution the default value of adc resolution is 10bit and can be changed to 8bit or 9bit by control the adc resolution control register ( adcres ). lowering adc resolution reduces the requi red minimum line time. when the number of effective output bits is reduced, upper n- bits of output ports are valid and lowe r bits always have values of ?0?. 2-2. correlated double sampling ( cds ) the analog output signal of each pixel includes some te mporal random noise caused by the pixel reset action
1/3 inch sxga cmos image sensor S5K3A1EA 23 0 5 10 15 20 25 30 35 40 45 0 163248648096112128 program m able gain control channel gain (db) 1 2 3 4 5 6 7 8 9 10 0 16 32 48 64 80 96 112 128 programmable gain control relative channel gain and some fixed pattern noise by the in-pixel amplifier offset deviation. to elimi nate those noise components, a correlated double sampling(cds) circuit is used before conver ting to digital. the output signal of each pixel is sampled twice, once for the reset level and once for the actual signal level. 2-3. programmable gain and offset control the user can controls the gain of indivi dual color channel by the programmable gain control registers ( pgcr , pgcg1 , pgcg2 , pgcb ) and offset by offset control registers ( offsr , offsg1 , offsg2 , offsb ). if the color channel separation mode is disabled ( ccsm =0), pgcg1 and offsg1 change the gains and offsets for all channels. as increasing the gain control register, the adc conv ersion input range decreases and the gain increases as following equation and the rela tive channel gain is shown in figure 3 channel gain = 128 / (128 ? pr ogrammable gain control register value[6:0]) figure 3. relative channel gain 2-4. quadrisectional global gain control the user can controls the global gain to change the gain for all color channels by the global gain control registers ( sgg1 , sgg2 , sgg3 , sgg4 ). the global gain control register is composed of four register groups and each register value decides the gain for each quarter section of output code level. at mclk=12mhz and ggo_en=l, the global gain is determined by the following formula. global gain = ( sgg [4:0]+1) / 16 r g1 g2 b r g1 g2 b r g1 g2 b r g1 g2 b
S5K3A1EA 1/3? sxga cmos image sensor 24 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0 4 8 121620242832 programmable gain control relative global gain -25 -20 -15 -10 -5 0 5 10 0 4 8 121620242832 programmable gain control global gain (db) figure 4. relative global gain the adc gain is dependent on mclk frequency (not on dclk frequency) and adc resolution. the default global gain is set for typical mclk frequency (12mhz) and 10-bit adc. when the frequency and adc resolution is changed, the global gain should be changed to maintain t he resulting gain over unity for assuring appropriate adc conversion range. the recommended minimum global gain setting depending on ggo_en and adcres is shown in figure 5 and table 2. 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 024681012141618202224262830323436384042444648 mclk frequency (mhz) minimum global gain figure 5. recommended minimum global gain control value (ggo_en = l) 8-bit adc resolution 10-bit adc resolution
1/3 inch sxga cmos image sensor S5K3A1EA 25 table 2. recommended minimum global gain setting (adcres = h) ggo_en = l ggo_en =h mclk [mhz] decimal hexadecimal decimal hexadecimal 6 31 1f - - 7 27 1b - - 8 23 17 - - 9 21 15 - - 10 19 13 - - 11 17 11 - - 12 15 0f 31 1f 13 14 0e 29 1d 14 13 0d 27 1b 15 12 0c 25 19 16 11 0b 23 17 17 11 0b 22 16 18 10 0a 21 15 19 10 0a 20 14 20 9 09 19 13 21 9 09 18 12 22 8 08 17 11 23 8 08 16 10 24 7 07 15 0f 25 7 07 15 0f 26 7 07 14 0e 27 7 07 14 0e 28 6 06 13 0d 29 6 06 13 0d 30 6 06 13 0c 30 6 06 13 0d 31 6 06 12 0c 32 5 05 11 0b 33 5 05 11 0b 34 5 05 11 0b 35 5 05 10 0a 36 5 05 10 0a 37 5 05 10 0a 38 5 05 10 0a 39 4 04 9 09
S5K3A1EA 1/3? sxga cmos image sensor 26 40 4 04 9 09 41 4 04 9 09 42 4 04 9 09 43 4 04 8 08 44 4 04 8 08 45 4 04 8 08 46 4 04 8 08 47 4 04 8 08 48 3 03 7 07 by appropriately programming these four register val ues, the different output resolution according to the signal can be achieved and the intra-scene dynamic range c an be increased by 16 times. in another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curve as shown in figure 6. figure 6. quadrisectional glabal gain control 255 0 511 767 1023 adc output code at 10-bit resolution sgg1=11111b sgg2=01111b sgg3=00111b sgg4=00011b adc input signal sgg1=01111b sgg2=01111b sgg3=01111b sgg4=01111b sgg1 sgg2 sgg3 sgg4
1/3 inch sxga cmos image sensor S5K3A1EA 27 3. post processing 3-1. dark level compensation the dark level of image sensor is defined as average out put level without illumination. it includes pixel ouput caused by leakage current of the photodi odes and adc offset. to compensate t he dark level, the output level of optical black(ob) pixels can be a good reference value. when auto dark level compensation register ( dlcm ) is set, the image sensor detects the ob pixel level at the start of every frame and anglog-to-digital conversion range is shifted to compensate the dark level for that frame. so, the resulting output data of that frame will be almost zero under dark state. if user wants the dark level which is not zero, the adc offset register ( adcoffs ) can be used. the lower 7-bit value represent the offset value in outout code for compensation and the msb is the sign to define whether the offset is positive ( adcoffs [7]=0) or negative ( adcoffs [7]=1). when not in auto dark level compensation mode, the adcoffs [7:0] act as a output code value to subt ract the output image data. please notify that the all the 8-bit data are used for an offset value without sign bit. adlc formula : d final = d(n) + adcoffs d(n) = (feed_gain_a)*(ob(n) + ob(n-1)) + (feed_gain_b)*d(n-1) 3-2. bad pixel replacement when the bad pixel replacement register ( bprm ) is enabled, the image sensor check that the image data is less or greater than horizontally neighboring pixels in same color channel by the preset threshold value ( pthresh ). if satisfied, the output of the pixel is replaced by t he averaged value of the neighboring two pixels. the detectable defected pixels are rare and the bad pixel replacement action can remove defected image effectively. but it reduces the line resolution in horizontal direction. 4. i 2 c serial interface the i 2 c is an industry standard serial interface. the i 2 c contains a serial two-wire half duplex interface that features bi-directional operation, master or slave mode. the general sda and scl are the bi-directional data and clock pins, respectively. these pins are open-drain type ports and will require a pull-up resistor to vdd. the image sensor operates in salve mode only and the scl is input only. the i 2 c bus interface is composed of following parts : start signal, 7-bit slave device addr ess (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the sl ave, 8-bit data transfer followed by an acknowledgement signal and stop signal. the sda bus line may only be changed while scl is low. the data on the sda bus line is valid on the high-to-low transition of scl .
S5K3A1EA 1/3? sxga cmos image sensor 28 figure 7. i 2 c bus write cycle figure 8. i 2 c bus read cycle sda start d 7 d 6 d scl ?0? ?0? ?1? ?0? ?0? ?0? ?1? i 2 c bus address i2c register address write ack ack sda scl d 7 d 6 dddddd data to write stop ack d d d d d sda start d 7 d 6 d scl ?0? ?0? ?1? ?0? ?0? ?0? ?1? i 2 c bus address i2c register address write ack ack stop d d d d d x sda re-start d 7 d 6 d scl ?0? ?0? ?1? ?0? ?0? ?0? ?1? i 2 c bus address data to be read read ack ack d d d d d
1/3 inch sxga cmos image sensor S5K3A1EA 29 timing chart vertical timing diagram continuous frame capture mode ( default case ) ( delayed vertical sync case) ( vertical data valid mode case) vsdisp=1 wrp(14th row) vsync hsync vswd (1row) wrd (1024 rows) vblank (101 rows) data 1 frame = wrd + vblank ( 1125 rows ) 10 rows = vsend_ofset 1 frame = wrd + vblank ( 1125 rows ) wrp(14th row) vsync hsync data vsstrt vswd 2rows 2rows 10 rows = vsend_ofset wrp(14th row) wrd (1024 rows) vblank (101 rows) vsync hsync (hsdisp=0) data hsync (hsdisp=1) 10 rows = vsend_ofset
S5K3A1EA 1/3? sxga cmos image sensor 30 vertical timing diagram (continued) ( short ob line & fixed vertical sync mode) isp_sel = 1& fix_vs = 1 ( short ob line & normal sync mode) isp_sel = 1, vsstrt = 1117d, vswd = 2d wrp(14th row) vsync hsync vswd (1row) wrd (1024 rows) vblank (101 rows) data 1 frame = wrd + vblank ( 1125 rows ) wrp(14th row) 4 rows = vsend_ofset normal frame output wrp(14th row) wrd (1024 rows) wrp(14th row) vblank (101 rows) data hsync vsync default vsync vsstrt (1117 rows) 4 rows = vsend_ofset vswd (2rows) normal frame output 1 frame = wrd + vblank ( 1125 rows )
1/3 inch sxga cmos image sensor S5K3A1EA 31 vertical timing diagram (continued) single frame capture mode ( rolling shutter case, sfcen = 1 & roll_mod = 1 ) ( mechanical shutter case, sfcen=1 & mech_mod = 1 ) normal frame output vsync hsync data strb integration time for 1st readout row integration time for 2nd readout row integration time for 3rd readout row integration time for 4th readout row sint x (1 row time) = integration time wrp(14th row) wrd (1024 rows) external mechanical shutter vsync hsync data strb can be opened should be closed wrd (1024 rows) wrp(14th row) normal frame output integration time for all pixels
S5K3A1EA 1/3? sxga cmos image sensor 32 ( global shutter case, sfcen=1 & global_mod = 1 ) vsync hsync data strb wrd (1024 rows) wrp(14th row) normal frame output integration time for all pixels
1/3 inch sxga cmos image sensor S5K3A1EA 33 horizontal timing diagram ( default case ) ( delayed horizontal sync case ) ( horizontal data valid mode case ) hsdisp=1 wcw 1 row = wcw + hblank hsstrt hsync vsync data dclk hswd wcw hsync vsync data dclk hblank wcw ( 1280 columns ) 1 row = wcw + hblank ( 1422 columns ) hswd hblank ( 142 columns ) hsync vsync data dclk wcp ( 14th column) 10 dclk
S5K3A1EA 1/3? sxga cmos image sensor 34 package dimension 48pin clcc (unit = mm) bottom view side view top view 0.51 0.08 r 0.15 4 corners 48 1 1.016 0.18 11.176 0.13 1.016 0.08 1.65 0.18 0.55 0.05 glass center of image area (x=+0.088 0.15, y=0.002 0.15 from package center) max. chip rotation = 1.5 degree max. chip tilt = 0.05mm 6 43 48 1 7 18 19 30 42 31 14.22sq +0.30/-0.13

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